Advanced Modelling Techniques in VHDL .ppt

Topics of the Lecture Packages USE clause Aliases Data alias Non-data alias Resolved signals Packages Packages Method for Grouping Related Declarations Which Serve a Common Purpose Set of subprograms to operate on particular data type Set of declarations for particular model Separate interface from implementation Reusable Packages Unclutter rest of model Allows declaration of “global” signals, e.g., clocks. Not a generally good since behavior can change through means other than signals declared in entity interface Packages Design Unit Similar to Entity Declarations and Architecture Bodies Can be put in library and made accessible to other units Access to items declared in the package is through using its Selected Name library_name.package_name.item_name Aliases can be used to allow shorter names for accessing declared items Packages Two Components to Packages Package declaration Package body Package Declaration Subprograms Using Header, Implementation Is Hidden “information hiding” Constants, Do Not Need to Be Initialized in Declaration “information hiding” Package Declaration Types, Must Be Completely Specified Can have variable size arrays Signals Must Be Completely Specified Package Declaration Syntax package identifier is package_declarative_item end [ package ] [ identifier ] ; Package Declaration Example* package dp32_types is constant unit_delay : Time : 1 ns ; type bool_to_bit_table is array boolean of bit ; . . . Package Declaration Example* function bits_to_int bits : in bit_vector return integer ; function bits_to_natural bits : in bit_vector return natural ; procedure int_to_bits int : in integer ; bits : out bit_vector ; end dp32_types ; Package Body Not Necessary If Package Declaration Does Not Declare Subprograms May Contain Additional Declarations Which Are Local to the Package Body Cannot declare signals in body Package Body Declared Subprograms Must Include the Full Declaration As Used in Package Declaration Numeric lit