Advancing RIT to Submicron Technology Design and Fabrication of.ppt

Chemical Mechanical Planarization of TEOS SiO2 for Shallow Trench Isolation Processes on an IPEC/Westech 372 Wafer Polisher Michael Aquilino Microelectronic Engineering Department Rochester Institute of Technology EMCR 801: MicroE Graduate Seminar October 17, 2005 * * Outline 2 STI vs. LOCOS Example STI Process CMP Equipment and Materials Westech 372 “How-To” CMP Results Process and Layout Challenges Questions 3 W WEFF W STI is replacement of LOCOS as preferred isolation technology STI vs. LOCOS Isolation Schemes STI WDRAWN ≈ WACTUAL Increased packing density Larger drive current for devices with same WDRAWN Decreased Topography LOCOS WEFF WDRAWN due to “Bird’s Beak” Effect Transistors must be made wider to achieve nominal drive current, decreased packing density Difficult to use LOCOS 0.5 μm Example STI Process 4 Grow 500A Pad Oxide Deposit 1500A Si3N4 by LPCVD Level 1 Lithography to protect Active areas with photoresist STI Trench Etch RIE in Drytek Quad Target: 4000A Si Trench 5 Remove photoresist Grow 500A Liner Oxide Repair damage to sidewalls Deposit 7000A TEOS SiO2 by PECVD in Applied Materials P5000 CMP TEOS with Westech 372 Nitride is stopping layer since CMP slurry removes oxide 4x faster then nitride Example STI Process 6 Densify TEOS in Bruce Furnace for 60 min @ 1000C in N2 Remove Nitride in Phosphoric Acid (H3PO4) @ 175C Many more steps . . . Final CMOS Cross Section Example STI Process CMP Equipment Schematic 7 8 Speedfam/IPEC/Westech Model 372 Note: The carrier oscillates as well as the table to improve uniformity Pads and Slurry 9 Current pad on Westech 372 is a Rodel CR IC1000-A2, 23” diameter Small circular pits for pattern. Others have rings, diamonds, checkerboard, etc Diamond grit pad conditioner will rough up surface of pad to increase friction with wafer and maintain etch rate and uniformity Slurries are colloidal silica particles of sub-micron size in KOH or NH4