2015 调研报告.pptVIP

总结 报告中介绍了关于TSV各方面特性的测试方法与测试结果。 （1）、通过kelvin 结构和矩阵结构测试TSV的低频特性，如电阻、合格率和漏电流等； （2）、利用电路的延时和谐振搭建电路来测试基于silicon interposer的TSV的延迟特性； （3）、介绍了两种TSV的高频模型，并对这两种测试结构进行简单分析和比较； （4）、考虑到TSV之间耦合效应的影响，对耦合效应可能带来的影响进行了简单的分析； （5）、介绍了关于3D TSV package 的热效应的测量与分析； （6）、从整体上介绍了3D IC测试的基本流程与面临的一些问题，以及on-chip Design-for-Testability (DfT)电路的简介。 3D-TSV 测试调研报告 马鹤 2011/8/13 3D stacked ICs To address the ever increasing need for low cost, high density devices a new industry design paradigm has emerged. 3D stacked IC (SIC) using Through Silicon Via (TSV) interconnects offers the opportunity to integrate multiple ICs at lower cost and silicon footprint than conventional System in Package (SiP) technologies. Due to the new advanced manufacturing processes and physical access limitations of the TSVs, it is necessary for us to know the new characterizations of the TSVs. Test Content Electrical Characterization of 3D TSV Ⅰ、TSV DC characterization Ⅱ、AC characterization Ⅲ、High frequency characterization Equivalent thermal conductivity of TSV Test for 3D chips Ⅰ、DC Characterization A. TSV resistance For an accurate measurement of TSV resistance, 4-point Kelvin resistor configurations are adopted DC Characterization isolated TSVs show some voids or interfaces between the TSV and the landing pad, which are affecting the TSV contact resistance. This problem is absent in the dense TSV structures; causes are still under investigation. DC Characterization B. TSV yield TSV matrix structures where each TSV in the array is accessible for electrical measurement have been implemented. DC Characterization Measurement results for a 8x8 TSV matrix with a) 10um and b) 20um pitch. TSV yield decreases with TSV pitch and is lower at the edge of both matrices. TSVs in the center of the array show a good contact with the landing pad; some Cu extrusion due to bonding is visible. A possible cause maybe occurs in the