01静态时序分析基本原理和时序分析模型.ppt

Reference Documents Quartus II Handbook, Volume 3, Chapter 7 The Quartus II TimeQuest Timing Analyzer /literature/hb/qts/qts_qii53018.pdf Quick Start Tutorial /literature/hb/qts/ug_tq_tutorial.pdf Cookbook /literature/manual/mnl_timequest_cookbook.pdf Reference Documents SDC and TimeQuest API Reference Manual /literature/manual/mnl_sdctmq.pdf AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer /literature/an/an481.pdf AN 433: Constraining and Analyzing Source-Synchronous Interfaces /literature/an/an433.pdf * * * * * * Relative to REG2 * Relative to REG2 * Relative to REG2 * Relative to REG2 * Relative to REG2 * * “Double-clocking” is when data arrival time is so low when compared to the clock arrival time that it is clocked through two subsequent register stages during one clock cycle * * * * Truly asynchronous paths cannot be analyzed for timing * * Speaker Note: “no sep model for rise / fall means that the slower is defined for slow corner model then the fast model (for stratix is defined by scaling that model. This means that the actual fastest path (rise or fall) may not be captured. Guardbanding is very important to catch this. * * * * ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation ? 2009 Altera Corporation * ? 2009 Altera Corporation Quartus? II Software Design Series: Timing Analysis - Timing analysis basics * Objectives Display a complete understanding of timing analysis * How does timing verification work? Every device path in design must be analyzed with respect to timing specifications/requirements Catch timing-related errors faster and easier than gate-level simulation board testing Designer must enter timing requirements exceptions Used to guide fitter during placement routing Used to compare