VHDL实例程序.doc

VHDL实例程序 重要说明：不同软件对VHDL语法的支持范围是不一样的，以下程序中的某些语句可能不能运行在所有的软件平台之上，因此程序可能要作一些修改，同时务必注意阅读程序中的注释。以下部分程序为txt格式，请自行另存为vdh后缀的文件。有些EDA软件要求ENTITY的名称和文件名要相同，也请自行修改。 如发现错误请来信指正或在BBS上提出。 计数器 -- n-Bit Synchronous Counter -- dowload from: LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY cntrnbit IS GENERIC(n : Positive := 8); PORT(clock, reset, enable : IN Std_logic; count : OUT Std_logic_vector((n-1) DOWNTO 0)); END cntrnbit; ARCHITECTURE v1 OF cntrnbit IS SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0); BEGIN PROCESS BEGIN WAIT UNTIL rising_edge(clock); IF reset = 1 THEN count_int = (OTHERS = 0); ELSIF enable = 1 THEN count_int = count_int + 1; ELSE NULL; END IF; END PROCESS; count = count_int; END v1; 8位总线收发器 -- Octal Bus Transceiver -- This example shows the use of the high impedance literal Z provided by std_logic. -- The aggregate (others = Z) means all of the bits of B must be forced to Z. -- Ports A and B must be resolved for this model to work correctly (hence std_logic rather than std_ulogic). -- download from: library IEEE; use IEEE.Std_logic_1164.all; entity HCT245 is port(A, B : inout std_logic_vector(7 downto 0); DIR, GBAR : in std_logic); end HCT245; architecture VER1 of HCT245 is begin A = B when (GBAR = 0) and (DIR = 0) else (others = Z); B = A when (GBAR = 0) and (DIR = 1) else (others = Z); end VER1; 高级优先级编程 -- Highest Priority Encoder -- download from LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity priority is port(I : in bit_vector(7 downto 0); --inputs to be prioritised A : out bit_vector(2 downto 0); --encoded output GS : out bit); --group signal output end priority; architecture v1 of priority is begin