VHDL整理.docVIP

VHDL重点 再度吐血——林新发 CPLD :Complex programmable logic devices (based on 乘积项) FPGA：Field Programmable Gate Array（based on LUT） PROM:与阵列固定，或阵列可编程(巧记，有个O，联想到or,所以是或) PLA：与或阵列均可编程（巧记，pla,两个音，所以与或都有） PAL，GAL：与阵列可编程，或阵列不可编程（巧记，一个音，是与） 6.Digital system design is based on programmable logic devices (PLD).It is top-down design,suing EDA. 7.VHDL Strong capability of system description Independence of device and hardware technique IEEE standard Flexible design method(behav,struc,dataflow) Readable program As an HDL,executed concurrently structurc of VHDL:（目测填空题） LIBRARY, Package, Entity, Architecture, Configuration, Block, Sub-program, Default Library（默认库）:STD,work MOD（取模），REM（取余），ABS（取绝对值），SLA（算数左移） SRA（算数右移），SRL（逻辑右移），SLL（逻辑左移），ROR，ROL Different package------different physic circuit; Entity-------outward appearence Architecture--------describe the function or structure of the circuit Input-------can not be assign the value Output------can not be the source of assignment Inout-------bi-directional port Buffer-------serve as an output,its value can be reloaded Architecture description Behavior description Data flow description Structure description 18.字符用’ ’,字符串用” ” 19.实体名不能用数字开头，实体名要与文件名一致 VHDL data type Integer, real, natural, bit, bit_vector, std_logic, std_logic_vector, character, string, boolean, time, severity level ’Z’ high impedance ‘X’ forcing unknown 自定义数组TYPE word8 IS ARRY (1 TO 8) OF BIT; VHDL data object: constant, variable, signal signal: 1.has corresponding hardware, 2.global,for multiple process 3.assignment has delay, 4.can carry history information 26.variable: 1.has no corresponding hardware 2.local,valid in its process only 3.assignment takes effect immediately 4.has current value only 27.sequential statements should be packaged in process 注意：if语句和case也可以相互改写，要根据题目改写，书写顺序要小心，特别是优先级编码器 PROCESS，注意，它是，只是它里面是 31.process的特点（一般是选择题） sequential statement(顺序语句)有if statement,case statement,loop statement,next statement,exit statement,wait sta