电子设计自动化EDA18437.ppt

* LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY one IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END one; ARCHITECTURE body_one OF one IS signal muxval : integer range 7 downto 0; BEGIN process(i0,i1,i2,i3,a,b) begin muxval = 0; if (a = 1) then muxval = muxval + 1; end if; if (b = 1) then muxval = muxval + 2; end if; case muxval is when 0 = q = i0; when 1 = q = i1; when 2 = q = i2; when 3 = q = i3; when others = null; end case; end process; END body_one; another * * RTL电路 * RTL电路 * LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY two IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END tw0; ARCHITECTURE body_two OF two IS BEGIN process(i0,i1,i2,i3,a,b) variable muxval : integer range 7 downto 0; begin muxval := 0; if (a = 1) then muxval := muxval + 1; end if; if (b = 1) then muxval := muxval + 2; end if; case muxval is when 0 = q = i0; when 1 = q = i1; when 2 = q = i2; when 3 = q = i3; when others = null; end case; end process; END body_two; front * * library ieee; use ieee.std_logic_1164.all; entity cntvh10 is port (nrst,en,clk: in std_logic; co: out std_logic; qout: out std_logic_vector(7 downto 0)); end cntvh10; * architecture arch of cntvh10 is component decoder48 port(num: in std_logic_vector(3 downto 0); en: in std_logic; decodeout: out std_logic_vector(7 downto 0)); end component; component cntm10 port(en,nreset,clk: in std_logic; co: out std_logic; qcnt: out std_logic_vector(3 downto 0)); end component; signal qa:std_logic_vector(3 downto 0); begin u1:cntm10 port map(en,nrst,clk,co,qa); u2:decoder48 port map(decodeout=qout,en=en,num=qa); end arch; decoder48 名称映射法 位置映射法 * 3.2.2 生成语句（GENER