《第10章Verilog硬件描述语言实例.ppt

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2016-12-29 发布于北京
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《第10章Verilog硬件描述语言实例.ppt

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S0: begin op =0; if (din==0) next_state = S0; else next_state = S1; end //第二个always进程——组合逻辑电路 always@(current_state or din) begin case( current_state ) Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. S1: begin op =1; if (din==1) next_state = S1; else next_state = S2; end Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. S2: begin op =0; if (din==1) next_state = S2; else next_state = S3; end Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. S3: begin op =0; if (din==0) next_state = S3; else next_state = S0; end Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. default: //case缺省项，防止产生锁存器 begin op =0; next_state = S0; end endcase end endmodule Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 　　　（4）Mealy型状态机的Verilog语言描述 Mealy型状态机结构图 Mealy型状态机状态图 Mealy型：输出是当前状态和输入的函数。 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. module mealy_machine(clk,din,op); input clk,din; output op; reg[1:0] current_state,next_state; reg op; parameter S0=2b00,S1=2b01,S2=2b10,S3=2b11; //第一个always进程——时序逻辑电路 always@( posedge clk) begin current_state = next_state; end Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. //第二个always进程 always@(current_state or din) begin case( current_state ) S0: begin if (din==0) begin next_state = S0; op =0; end else begin next_state = S1; op =1; end end Evaluation only. Created with Aspose.Slides for .NET 3.5 Cli