南京理工EDA2多功能电子时钟(VHDL语言版)..docx

EDAⅡ实验报告作者:诗意情缘学 号：9121xxxxx学院:电子工程与光电技术学院专业(方向):微电子学题目:基于QuatusⅡ的多功能数字钟设计 指导者：姜X评阅者：姜X 2014 年 12 月摘要数字钟在生活中有着广泛的应用，其实现方式也是多种多样。本文基于QuatusⅡ在FPGA上用VHDL语言编程实现数字钟，其具有24小时计时，对时钟的时分秒进行校对，时钟保持，时钟清零，整点报时，设置闹钟功能。为方便使用，在校对的时间进行闪烁显示，闹钟时进行音乐播放。本文采用自顶向下的模块式设计方法，将整个电路分为控制模块、分频模块、计时校分模块、闹钟定时模块、报时音乐模块、闪烁模块、显示模块。在设计时对每个模块所需要的功能进行仿真验证或直接下载到实验平台验证。在验证了功能的正确性后，将各个模块相互连接组成一个总的电路。最后对总的电路分配好引脚，下载到实验板上，在满足基本功能的情况下进行了微创新，达到了不错的效果。关键词：EDA FPGA 多功能数字钟AbstractDigital clock has been widely used in our daily life, the way of its implementation is also varied.This paper describes how to realize digital clock based on Quatus Ⅱ on FPGA with VHDL language programming.It is a 24-hour timer with multiple functions such as checking hour or minute or second of the clock ,resetting the clock , telling the time on the hour ,setting the alarm clock. As a matter of convenience , the Nixie tube gives a blinking display while checking the time , and when it is time to alarm ,it will play a song named Ten Years. This paper adopts a method of the top-down modular design. The whole circuit can be divided into several sub-modules: control module, the frequency- division module, timing module, alarm-clock module, the timing-music module, the module, blinking module, display module.After finishing the design of each sub-module, we check functions to see whether the module works exactly correct with the help of simulator or downloading the design directly into development platform. Having validate functions of each module,they are interconnected to form a general circuit.Finally, allocate pins for the inputs and outputs of the overall circuit, download the design into development platform. It perfects very good with some basic functions and some micro-innovative functions.Key words: EDA FPGA Multi-function digital clock一、主要功能1.1设计基本功能①能进行正常的时、分、秒计时②分别由六个数码显示时分秒的计时③具有使能开关，可使时钟保持不变④具有清零开关，可使时钟时、分、秒清零⑤具有校对时间功能，可快速调整时钟的时、分、秒1.2改进与提高①具有整点报时功能②界面人性化，时分秒短横线间隔显示，校对时间相应位闪烁显示③增加闹钟设置功能，并播放音乐《十年》④可手动关闭音乐二、设计方案实验平台：软件：Windo