下面程序是1位十进制计数器的VHDL描述..doc

下面程序是1位十进制计数器的VHDL描述，试补充完整。 2. 下面是一个多路选择器的VHDL描述，充完整。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT ( CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ; END CNT10; ARCHITECTURE bhv OF CNT10 IS SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN -- 边沿检测 IF Q1 10 THEN Q1 = (OTHERS = 0); -- 置零 ELSE Q1 = Q1 + 1 ; -- 加1 END IF; END IF; END PROCESS ; Q = Q1; END bhv; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmux IS PORT ( sel : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)) ; END bmux; ARCHITECTURE bhv OF bmux IS BEGIN y = A when sel = 1 ELSE B; END bhv; 三、VHDL程序改错 仔细阅读下列程序，回答问题 LIBRARY IEEE; -- 1 USE IEEE.STD_LOGIC_1164.ALL; -- 2 ENTITY LED7SEG IS -- 3 PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- 4 CLK : IN STD_LOGIC; -- 5 LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); -- 6 END LED7SEG; -- 7 ARCHITECTURE one OF LED7SEG IS -- 8 SIGNAL TMP : STD_LOGIC; -- 9 BEGIN -- 10 SYNC : PROCESS(CLK, A) -- 11 BEGIN -- 12 IF CLKEVENT AND CLK = 1 THEN -- 13 TMP = A; -- 14 END IF; -- 15 END PROCESS; -- 16 OUTLED : PROCESS(TMP) -- 17 BEGIN -- 18 CASE TMP IS -- 19 WHEN 0000 = LED7S = 0111111; -- 20 WHEN 0001 = LED7S = 0000110; -- 21 WHEN 0010 = LED7S = 1011011; -- 22 WHEN 0011 = LED7S = 1001111; -- 23 WHEN 0100 = LED7S = 1100110; -- 24 WHEN 0101 = LED7S = 1101101; -- 25 WHEN 0110 = LED7S = 1111101; -- 26 WHEN 0111 = LED7S = 0000111; -- 27 WHEN 1000 = LED7S = 1111111; -- 28 WHEN 1001 = LED7S = 1101111; -- 29 END CASE; -- 30 END PROCESS; -- 31 END one; -- 32 在程序中存在两处错误，试指出，并说明理由： 第14行 TMP附值错误 第29与30行之