《EDA实验.docVIP

四选一多路选择器三种方法 module MUX41a(a,b,c,d,s1,s0,y); input a,b,c,d; input s1,s0; output y; reg y; always@(a or b or c or d or s1 or s0); begin : MUX41 case ({s1,s0}) 2b00: y=a; 2b01: y=b; 2b10: y=c; 2b11: y=d; default: y=a; endcase end endmodule module MUX41a (a,b,c,d,s1,s0,y); input a,b,c,d,s1,s0; wire[1:0] SEL; wire AT,BT,CT,DT; assign SEL={s1,ss0}; assign AT=(SEL==2D0); assign BT=(SEL==2D1); assign CT=(SEL==2D2); assign DT=(SEL==2D3); assign y=(aAT)|(bBT)|(cCT)|(dDT); endmodule  module mux41a(A,B,C,D,S1,S0,Y); input A,B,C,D,S1,S0; output Y; wire AT=S0?D:C; wire BT=S0?B:A; wire Y=(S1?AT:BT); endmodule vlib work vlog ../rtl/mux41a.v vlog ../tb/mux41a_tb.v vsim mux41a_tb  `timescale 1ns/1ps module mux41a_tb; reg A,B,C,D,S1,S0; //always@(A or B or C or D or S1 or S0) // begin : mux41 //case({S1,S0}) initial begin S1= 1b1; S0= 1b0; A=1b1; B=1b0; C=1b1; D=1b0; #5; S1= 1b0; B=1b1; C=1b0; #5; S0= 1b1; A=1b0; D=1b1; #5; S1= 1b1; B=1b0; C=1b1; #5; //endcase end mux41a s_mux41a ( .A(A), .B(B), .C(C), .D(D), .S1(S1), .S0(S0), .Y(Y) ) ; endmodule  半加器 module h_adder(A,B,SO,CO); input A,B; output SO,CO; assign SO=A^B; assign CO=AB; endmodule vlib work vlog ../rtl/h_adder.v vlog ../tb/tb.v vsim tb #run 25ns  `timescale 1ns/1ps module tb; reg A,B; initial begin A= 1b1; B= 1b0; #5; A= 1b0; #5; B= 1b1; #5; A= 1b1; #5; end wire CO,SO; h_adder m_adder ( .A(A), .B(B), .SO(SO), .CO(CO) ) ; endmodule  计数器 module CTR (CLK,Q,R); input CLK,R; output[3:0]Q; reg[3:0] Q; always @(posedge CLK or negedge R) if(!R) Q=0; else Q=Q+4b0001; endmodule vlib work vlog ../rtl/CTR.v vlog ../tb/tb.v vsim tb  `timescale 1ns/1ps module tb; reg CLK,R; initial begin CLK=1b0; R=0; #5 CLK=1b1; R=1; #5 R=1; C