《VHDL实例演示程序.docVIP

组合逻辑电路的设计实例 与非门 加法器 编码器 译码器 数据选择器 练习题：2输入异或门、数据分配器 三输入“与非”门电路 1）数据流描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand3 IS PORT (a, b, c: IN BIT; y: OUT BIT); END nand3; ARCHITECTURE rtl OF nand3 IS BEGIN y = NOT (a AND b AND c); END rtl; 2）行为描述1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand3 IS PORT (a, b, c: IN BIT; y: OUT BIT); END nand3; ARCHITECTURE behave OF nand3 IS BEGIN PROCESS (a, b, c) BEGIN IF (a = 1 AND b= 1 AND c = 1) THEN y = 0; ELSE y = 1; END IF; END PROCESS; END behave; 3）行为描述2——真值表 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand3 IS PORT (a, b, c: IN BIT; y: OUT BIT); END nand3; ARCHITECTURE behave2 OF nand3 IS BEGIN PROCESS (a, b, c) VARIABLE tmp: BIT_VECTOR (2 DOWNTO 0); BEGIN tmp: = a b c; CASE tmp IS WHEN 000 = y = 1; WHEN 001 = y = 1; WHEN 010 = y = 1; WHEN 011 = y = 1; WHEN 100 = y = 1; WHEN 101 = y = 1; WHEN 110 = y = 1; WHEN 111 = y = 0; END CASE; END PROCESS; END behave2; 4）结构描述方式 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand3 IS PORT (a, b, c: IN BIT; y: OUT BIT); END nand3; ARCHITECTURE structure OF nand3 IS SIGNAL temp: BIT; COMPONENT and3 IS PORT (a1, b1, c1: IN BIT; y1: OUT BIT); END COMPONENT; COMPONENT inv IS PORT (a2: IN BIT; y2: OUT BIT); END COMPONENT; BEGIN u1: and3 PORT MAP (a, b, c, temp); u2: inv PORT MAP (temp, y); END structure; 加法器 见第三章描述方式：三种描述方式描述全加器。 优先编码器 8线-3线优先编码器：若8输入中的一个输入有效（低电平有效），则此输入对应的3位二进制编码输出；若多个输入有效，则输出优先级高的输入对应的编码。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY priorityencoder IS PORT (i: IN STD_LOGIC_VECTOR (7 DOWNTO 0); y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END priorityencoder; ARCHITECTURE archi OF priorityencoder IS BEGIN PROCESS (i) BEGIN IF (i (0) = 0 ) THEN y = 111; ELSIF (i (1) = 0) THEN y = 110; ELSIF (i (2) =