北理工Quartus实验二报告.docx

实验二模十状态机与7段译码器显示一、实验目的：通过设计频率可选的模十状态机以及7段译码电路以进一步掌握VHDL硬件描述语言。二、实验流程：本设计有分频器、多路选择器、状态机和译码器。1.时钟输入作为分频器的输入，输出时钟分别为2分频、4分频、8分频和16分频；2.四个频率的时钟信号由4选1的多路选择器选择其中之一作为状态机的时钟输入；3.使用选中的时钟频率作为输入驱动状态机按照以下的次序输出：0-2-5-6-1-9-4-8-7-3-0的顺序输出；4.使用此输出作为驱动输入到7段译码器的显示逻辑。三、实验代码：library IEEE;use IEEE.std_logic_1164.all;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mod10 isport(clk,rst,load:in std_logic;sel:in std_logic_vector(1 downto 0);countss:in std_logic_vector(3 downto 0);seg:out std_logic_vector(6 downto 0));end mod10;architecture beha of mod10 is signal clk1,clk2,clk4,clk8,clk16:std_logic; signal count,q_temp:std_logic_vector(3 downto 0); signal counts:std_logic_vector(3 downto 0):=0000;begin process(clk,rst) --分频、rst:清零，低有效 begin if( rst = 0) thencount =0000; elsif( clkevent and clk =0) then count = count+1; end if; clk2 = count(0); clk4 = count(1); clk8 = count(2); clk16 = count(3); end process;process(sel) --选择时钟信号是几分频 begincase sel iswhen 00 = clk1 = clk2;when 01= clk1 = clk4;when 10 = clk1 = clk8;when 11 = clk1 = clk16;when others = null; end case;end process;process(clk1,rst,load) --load：置数，高有效， beginif(rst=0)then counts=0000;elsif(load=1)thencounts=countss;elsif( clk1event and clk1 =0) thencase counts is --改变出来的数的顺序when0000=counts=0010;when0010=counts=0101;when0101=counts=0110;when0110=counts=0001;when0001=counts=1001;when1001=counts=0100;when0100=counts=1000;when1000=counts=0111;when0111=counts=0011;when0011=counts=0000;when others=counts=0000;end case;end if;q_temp=counts;end process;process(q_temp) --7段发光二极管begincase q_temp iswhen0000=seg=1000000;--40h,79h,24h,30h,19h,12h,02h,78h,00h,10hwhen0001=seg=1111001;when0010=seg=0100100;when0011=seg=0110000;when0100=seg=0011001;when0101=seg=0010010;when0110=seg=0000010;when0111=seg=1111000;when1000=seg=0000000;when1001=seg=0010000;when others=seg=0001000;end case;end process;end beha;四、实验结果1、功能仿真整体结果：二分频：四分频：八分频：十六分频：2、时序仿真整体结果：二分频：四分频：八分频：十六分频：五、实验心得：做这个实验