实验八利用有限状态机进行时序逻辑的设计.doc

实验八：利用有限状态机进行时序逻辑的设计 一：利用有限状态机进行时序逻辑的设计的源程序: module seqdet(x,z,clk,rst,state); input x,clk,rst; output z; output[2:0] state; reg[2:0] state; wire z; parameter IDLE=d0, A=d1, B=d2, C=d3, D=d4, E=d5, F=d6, G=d7; assign z = ( state==E x==0 )? 1 : 0; always @(posedge clk) if(!rst) begin state = IDLE; end else casex(state) IDLE : if(x==1) begin state = A; end A: if(x==0) begin state = B; end B: if(x==0) begin state = C; end else begin state = F; end C: if(x==1) begin state = D; end else begin state = G; end D: if(x==0) begin state = E; end else begin state = A; end E: if(x==0) begin state = C; end else begin state = A; end F: if(x==1) begin state = A; end else begin state = B; end G: if(x==1) begin state = F; end default:state=IDLE; endcase endmodule 二：利用有限状态机进行时序逻辑的设计的测试代码： `timescale 1ns/1ns `include ./seqdet.v module seqdet_Top; reg clk,rst; reg[23:0] data; wire[2:0] state; wire z,x; assign x=data[23]; always #10 clk = ~clk; always @(posedge clk) data={data[22:0],data[23]}; initial begin clk=0; rst=1; #2 rst=0; #30 rst=1; data =b1100_1001_0000_1001_0100; #500 $stop; end seqdet m(x,z,clk,rst,state); endmodule 三：Transcript显示结果： # Reading E:/altera/91/modelsim_ase/tcl/vsim/pref.tcl # Loading project fulladder8 # reading E:\altera\91\modelsim_ase\win32aloem/../modelsim.ini # Loading project ssss # Compile of seqdet.v was successful. # Compile of seqdet_Top.v was successful. # 2 compiles, 0 failed with no errors. vsim work.seqdet_Top # vsim work.seqdet_Top # Loading work.seqdet_Top # Loading work.seqdet 四：测试波形如下图所示：