CypressRAMFAETrain.pptVIP

Cypress APAC Memory TrainingSpring, 2004 Main Agenda Asynchronous /Synchronous SRAM Networking Memory Evolution Fast Asynchronous SRAM Asynchronous operation (No presence of a clock) Read/Write operation done using control pins such as ‘/CE’, ‘/WE’ and ‘/OE’. /CE signal is used to activate or deactivate the SRAM. This signal makes the other signals inactive when deselected. /WE signal is used to select between a READ or a WRITE operation. A low on /WE signal signifies a write operation. /OE signal is used to drive the data onto the data bus from the memory array of the SRAM in the READ mode. Fast Asynchronous SRAM Fast Asynchronous SRAM Fast Asynchronous SRAM Fast Asynchronous SRAM Target Application PC Cache DSP Interface Memory Buffer Wireless Devices Fast Asynchronous SRAM Broadest Industry Product Portfolio and Expanding New Products: 8M, 12M, 16M New Packages: FBGA on 0.15m 2/4/8/12/16M, 300Mil 1M SOJ, TQFP 2M Speed Leadership: 8ns on 3V 1 4Ms Automotive Temp: 256K, 1M, 4M Continuous Investment in Design and RD Ramping up on 90nm Technology Long-Term Product Support Customer Will EOL Before Us Continuous Support of Low Density 5V Products Still Support 4 Kb SRAMs! Sync SRAM Family Standard Sync SRAMs NoBL SRAMs QDR /QDR II DDR /DDR II NetRAM Standard Sync SRAM Synchronous SRAM Flowthrough Timing Diagram Pipelined Timing Diagram SCD v/s DCD SCD – Single-Cycle Deselect One clock cycle until chip deselects Available in Pipelined and Flowthrough DCD – Double-Cycle Deselect Two clock cycles until chip deselects Available in Pipelined only Flowthrough vs. Pipeline NoBL? SRAMs What is NOBL ? Flowthrough NoBL Operation Pipelined NoBL Operation Standard Sync Vs NoBL TYPICAL SWITCH APPLICATION QDR QDRI Burst of 2 BLOCK DIAGRAM QDRI Burst of 4 BLOCK DIAGRAM QDR Advantages Features Benefits * Simultaneous Accesses * Improved Bandwidth(~2x) * DDR Interface on Both Ports * Improved Bandwidth(~2x) * Pipeline Output * Low