练习.docVIP

练习十二 利用SRAM设计一个FIFO //-------------------------------- 文件名：t.v -------------------- `define FIFO_SIZE 8 `include “sram.v” // 有的仿真工具不需要加这句, 只要sram.v模块编译过就可以了 `timescale 1ns/1ns module t; reg [7:0] in_data; //FIFO数据总线 reg fiford,fifowr; //FIFO控制信号 wire[7:0] out_data; wire nfull, nempty; //FIFO状态信号 reg clk,rst; wire[7:0] sram_data; //SRAM数据总线 wire[10:0] address; //SRAM的地址总线 wire rd,wr; //SRAM读写控制信号 reg [7:0] data_buf[`FIFO_SIZE:0]; //数据缓存，用于结果检查 integer index; //用于读写data_buf的指针 //系统时钟 initial clk=0; always #25 clk=~clk; //测试激励序列 initial begin fiford=1; fifowr=1; rst=1; #40 rst=0; #42 rst=1; if (nempty) $display($time,Error: FIFO be empty, nempty should be low.\n); //------------连续写FIFO ------- index = 0; repeat(`FIFO_SIZE) begin data_buf[index]=$random; write_fifo(data_buf[index]); index = index + 1; end if (nfull) $display($time,Error: FIFO full, nfull should be low.\n); repeat(2) write_fifo($random); #200 //----------连续读FIFO------------- index=0; read_fifo_compare(data_buf[index]); if (~nfull) $display($time,Error: FIFO not full, nfull should be high.\n); repeat(`FIFO_SIZE-1) begin index = index + 1; read_fifo_compare(data_buf[index]); end if (nempty) $display($time,Error: FIFO be empty, nempty should be low.\n); repeat(2) read_fifo_compare(8bx); reset_fifo; //------写后读FIFO------ repeat(`FIFO_SIZE*2) begin data_buf[0] = $random; write_fifo(data_buf[0]); read_fifo_compare(data_buf[0]); end