HDS服务器产品技术回顾及市场定位.ppt

The QPI interconnects at the top of this diagram depict that each processor is directly connected to every other processor in the merged blade set. Therefore the maximum memory latency is a single processor hop if the data requested resides in a memory bank that is directly connected to a different processor than the requesting one. This is a NUMA memory scheme but the default memory scheme is SMP. This can be changed for each blade via the blade management browser interface. The physical processor set can be configured in a variety of ways Dedicated cores, shared cores and core groupings. Physical memory is always dedicated to the LPAR upon activation Memory can be over-subscribed at the configuration level; however, if a memory block equal to or greater than that specified for the LPAR at activation time, then that LPAR will not start. PCIe cards can be either dedicated or shared. If dedicated, the entire card is dedicated. Separate timers are kept by the HVM for each active LPAR. The physical processor set can be configured in a variety of ways Dedicated cores, shared cores and core groupings. Physical memory is always dedicated to the LPAR upon activation Memory can be over-subscribed at the configuration level; however, if a memory block equal to or greater than that specified for the LPAR at activation time, then that LPAR will not start. PCIe cards can be either dedicated or shared. If dedicated, the entire card is dedicated. Separate timers are kept by the HVM for each active LPAR. * * BSMS is also required for N_M Failover. It is used to configure the active/standby pools and will assign the failover blade to begin the process once notified of a server failure by the SVP. Can failover to a blade in the same or different chassis. Permits hardware to be repaired in minutes instead of hours and or days. Requires a SAN environment because the standby blade will boot from and access the same LUNs as the original server. Requires virtualized WWNs for b