多功能数字钟论文带程序.doc

EDA2 多功能数字钟 院系： 学号： 912000720 姓名: 同组人： 指导老师： 时间： 2014 年 11 月 摘要 本实验通过使用 QuartusⅡ7.1软件，并结合verilog语言的知识设计多功能数字钟，可以实现正常的时、分、秒的计数功能，分别由六个数码管显示计时，可以利用开关实现系统的计时保持、清零和校分、校时的功能。同时，该电路系统还可以完成在 5953, 5955, 5957 低音报时, 5959 高音报时的基本功能。在此基础上，该电路还实现了设定闹钟，定时叫醒，和关闭闹钟的功能，在利用 QuartusⅡ进行相应的设计、仿真、调试后下载到EP3C25F324C8实验系统上，验证设计的正确性。 关键词 QuartusII，数字钟，Verilog HDL，分层设计 Abstract This experiment is based on QuartusⅡ 7.1，with the knowledge and system design, to design a multifunctional digital clock. The basic function of the multifunctional digital clock is a 24-hour timer, and the exact time can be showed by six LED lights. Also we can achieve the functions like time keeping, clearing and time and week adjusting by using the switches. Beyond the basic function, I improved the multifunctional digital clock and it can beep in low frequency at 5953 , 5955 , 5957 and in high frequency at 5959. Based on this the basic design, I also design extra functions of alarm, whose time can be adjusted by switch. It can also be turned off by switch. All these designing and simulating work are based on QuartusⅡ. After all the work finished on computer, I downloaded the final circuit to EP3C25F324C8 experiment system to test the accuracy of the design. Key words QuartusⅡ, Digital clock , Verilog HDL, Layered designing  目录 一、设计要求…………………………………………………………………… 二、分层设计及其分工……………………………………………………………………...........3 三、多功能数字时钟顶层设计…………………………………………………...........................4 四、各子模块设计原理及程序…………………………………………...................................…5 4.1 分频电路…………………………………………………..............................................……5 4.2 计数器……………………………………………………………..........................................6 4.3 计时电路………………………………………......................................……………………8 4.4 整点报时……………………………………..........................................................…………9 4.5 LED电路…………………………………………….....................................………………10 4.6 定