DLL在FPGA时钟设计中的应用.doc

DLL在FPGA时钟设计中的应用?[折叠] Abstract：The paper introduces a digital circuit dedicated to on-chip Delay-locked loop (DLL)，which provides zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control ..The DLL can provide multiple phases of the source clock but also can double or divide the frequency of the source clock. These functions can be implemented with hardware language using ISE design tools. In this way the clock quality can be improved and the PCB board design becomes simple. 随着FPGA尺寸的增加,芯片上时钟的分布质量就变得越来越重要。时钟相位差和时钟延迟严重影响设备的性能,在大的设备中,用传统的时钟网络控制时钟相位差和时钟延迟变得十分困难。在FPGA 设计中,延迟锁相环DLL (Delay Locked Loop) 是一种很好的资源,可实现对时钟的零延时或倍频、分频输出,特别是较高频率的时候,可以简化FPGA的设计。Xilinx公司在Virtex E、Spartan II 和Spartan IIE 系列芯片中,一直采用DLL技术进行内部时钟控制。时钟的设计和使用是非常重要的,采用可靠的时钟是保证设计可靠性的重要前提。 延迟锁相环DLL SpartanⅡ系列提供4个延迟锁相环DLL ,其分别位于芯片内部的4个脚。Delay-Locked-Loop (DLL) circuits in the Spartan-II FPGAs provide zero propagation delay and low clock skew between output clock signals distributed throughout thedevice. Each Spartan-II device has four fully digital dedicated on-chip DLLs, allowing for very precise synchronization of external and internal clock。Each DLL can drive up to two global clock routing networks within the device. The global clock distribution network minimizes clock skews due to loading differences. By monitoring a sample of the DLL output clock, the DLL can compensate for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device. In addition to providing zero delay with respect to a user source clock, the DLL can provide multiple phases of the source clock. The DLL can also act as a clock doubler or it can divide the user source clock by up to 16. Clock multiplication gives the designer a number of design alternatives. For instance, a 50 MHz source clock doubled by the DLL can drive an FPGA design operating at 100 MHz. This technique ca