BITKOGGESTONETREEADDER.pptVIP

16 BIT KOGGE-STONE TREE ADDER Shayan Kazemkhani Nghia Do Jia Kang Yu Toan Luong Agenda Abstract Introduction Why Tree Adder? Theory Project Details Summary of Results Lessons Learned Cost Analysis Conclusion Abstract We designed 16 bit Kogge-Stone Tree Adder - the most commonly used parallel prefix carry-lookahead adder topology. 200MHz clock frequency Area 1000*600 um^2 Power density AMI06 Technology Introduction Why? - minimum logic depth, wide wiring channels, regular structure and large fanout points. Prefix Adder Structure PROJECT DETAILS BLOCK DIAGRAM Longest path calculation Table of actual Wn Wp Schematic Layout DRC Report Extraction report LVS Report Cost Analysis Lessons Learned Start early Work in group Study previous projects Seek advice from Dr. Parent and previous students Save time for debugging error Conclusions We designed and implemented a 16 bit Kogge-Stone Tree Adder that operates at 200MHz in an area of 1000*600 um^2 Acknowledgements Thanks to Cadence Design Systems for the VLSI lab Thanks to Dr. David Parent Thanks to all 166, 167, and 224 students * Advisor: David Parent May 8th 2006 17 pin outs 33 input D-flip flops and 17 output D-flip flops Create schematic and layout for 16 bit tree adder Test schematic using test bench Run DRC and LVS to verify the design Tphl = 5ns/(14+3) = .29ns Estimate amount of time spent on project: - Verifying NC Verilog 5 hrs - Verifying Timing 10 hrs - Layout 40 hrs - Post Extracted Timing 10 hrs