DRunBSiliconElectronicsAndreiNomerotskiFermila.pptVIP

D0 Run 2B Silicon Electronics  Andrei Nomerotski, Fermilab December 3rd 2001, Technical Design Review Goals SVX4 chip Overview of Run 2B readout Analog flex cable Hybrids Interfacing to Run 2A readout Performance issues Summary Goals Robust system based on new SVX4 chip Run 2A readout Minimize time, effort and cost Minimum RD Recycle Run 2A readout as much as possible Conservative, low risk solutions Simple production, testing and commissioning Use Run2A commissioning experience SVX4 Chip New chip : SVX4 Designed by Fermilab/LBL/Padua 0.25 mm technology, intrinsically radiation hard Based on SVX3, compatible with SVX2 Several new schematics solutions D0 will use differential readout Use the same pad ring as CDF D0 DAQ can operate with SVX3 chips D0 DAQ was designed for SVX2 Some remapping of control signals is required Tested in Nov 2000, one SVX3 chip was read out with D0 Sequencer SVX4 Chip SVX4 Chip Test chip submitted to MOSIS in June 2001, back in August 16 channels LBL design preamp + pipeline 48 channels FNAL design preamp + pipeline Common bias preamp + pipeline as in SVX3 12 different input transistor sizes used to optimize noise Results: Optimum preamp ENC = 450e + 43.0e/pF Pipeline works Excellent radiation hardness Full chip layout and simulation in progress Submission of prototypes Dec 21st 2001 Two versions for prototyping Conservative On-chip bypassing of analog voltage Chips available for tests in March 2002 Joint test effort of CDF D0 at LBL and Fermilab Important to test prototypes as extensively as possible Second prototype submission will get the chip on the critical path! Production run planned in July 2002 Silicon Detector Layout Layers 1 - 5 Readout Layer 0 Readout Cable Count Changes of Run 2A Readout Signal level translation 5 V – 2.5 V Tight spec on 2.5 V (2.25 – 2.75 V) = Voltage regulation Mapping between SVX4 and SVX2 Differential / Single-E