数字逻辑电路设计-多功能数字钟.doc

数字逻辑电路设计-多功能数字钟 多功能数字钟 摘要：实验作品名为多功能数字钟，具有校时、清零、保持、整点报时、闹钟五大功能。整个实验以QuartusII 7.0为软件设计基础，结合Altera公司研发的Cyclone系列可编程逻辑器件工具箱进行实际测试。整个数字钟的开发完全遵照自顶向下的设计方法，这个设计因为该方法可移植性强、逻辑符合一般规律、可多人共做等优点而得以为设计人员省去大量时间和精力。本作品在防抖动电路和蜂鸣器鸣响时长控制上拥有一定的自主创新性和理论证明，同时由于整个设计过程当中适当地对每个器件进行了有机的封装，所以电路图的逻辑关系较为清晰。现在数字钟因其在日常生活生产中的作用而成为可盈利的商品，在金钱的驱动下数字钟的设计方法与本实验作品相比功能和效率上都有非常大的提升，故本实验的目的在于让设计者充分了解数字逻辑电路设计的流程和具体软件的使用方法。 关键词：数字钟，可编程逻辑器件，防抖动电路，学习型设计 The design of Multifunctional digital clock Abstract: This experimental product is called Multifunctional digital clock. It has five major functions such as time setting, resetting, holding, alarming, and beeping when it comes to an addition to the hour. The whole experiment is based on the software of design called Quartus II 7.0 and is tested by combining the Cyclone series of programmable logical device provided by Altera. The clock is designed under the process of ‘from the top to the end’. The method spares designers lots of time and energy for its flexibility to be transplanted, easiness for ordinary logic reasoning and availability for cooperative designing. The product is self-creative and provable in terms of turbulence muting and manipulation of the period of beeping. At the same time, the diagrams of the circuits are apparently logical thanks to well-organized sealing of each part of device during the design. In this era of common concept of inexpensiveness of digital clocks, methods and effectiveness of designing a clock are improved due to its profitability. Hence, this experimental design is aimed at letting the participants to understand the process of digital logic circuits designing and to get to familiar with the usage of particular software. Keyword: Digital Clock, programmable logic device, mute circuit, design for learning 目录 设计要求与说明………………………………………………………….4 方案论证……………………………………………………………………..4 1.设计整体思路 2.设计大体流程 三．各子模块设计原理与调试仿真………………………………….5 1.时钟发生器……………………………………………………………5 2.计时电路……