EDA实验代码.docx

EDA实验代码实验一：一位全加器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY adder1 ISPORT(A,B,C:IN STD_LOGIC; COUT,SUM:OUT STD_LOGIC);END ENTITY adder1;ARCHITECTURE hl OF adder1 ISSIGNAL ABC:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINABC=ABC;PROCESS(ABC)BEGINCASE ABC ISWHEN000=COUT=0;SUM=0;WHEN001=COUT=0;SUM=1;WHEN010=COUT=0;SUM=1;WHEN011=COUT=1;SUM=0;WHEN100=COUT=0;SUM=1;WHEN101=COUT=1;SUM=0;WHEN110=COUT=1;SUM=0;WHEN111=COUT=1;SUM=1;WHEN OTHERS=NULL;END CASE;END PROCESS;END ARCHITECTURE hl;四位全加器（需要调用）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY adder4 ISPORT (Ain, Bin: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ;END ENTITY adder4;ARCHITECTURE hl4 OF adder4 ISCOMPONENT adder1PORT (A, B, C: IN STD_LOGIC;SUM,COUT: OUT STD_LOGIC ) ;END COMPONENT;SIGNAL net1,net2,net3:STD_LOGIC;BEGINu1: adder1 PORT MAP(A=Ain(0),B=Bin(0),C=0,SUM=DOUT(0),COUT=net1);u2: adder1 PORT MAP(A=Ain(1),B=Bin(1),C=net1,SUM=DOUT(1),COUT=net2);u3: adder1 PORT MAP(A=Ain(2),B=Bin(2),C=net2,SUM=DOUT(2),COUT=net3);u4: adder1 PORT MAP(A=Ain(3),B=Bin(3),C=net3,SUM=DOUT(3),COUT=DOUT(4));END ARCHITECTURE hl4;实验二LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;USE IEEE.STD_LOGIC_ARITH.ALL ;ENTITY LED ISGENERIC ( T : INTEGER :=;PORT (CLK : IN STD_LOGIC ; Hz1 : OUT STD_LOGIC) ;END ;ARCHITECTURE bhv_HL OF LED ISSIGNAL Q : INTEGER RANGE 0 TO T-1;SIGNAL M : STD_LOGIC ;BEGINPROCESS (CLK,Q)BEGINIF FALLING_EDGE(CLK) THENIF (Q=0) THEN Q=T-1;ELSE Q=Q-1; END IF;IF (Q=0)THEN M=NOT M; ELSIF (Q=T/2)THEN M=NOT M;END IF;END IF;END PROCESS; Hz1=M;END bhv_HL;实验三LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;USE IEEE.STD_LOGIC_ARITH.ALL ;ENTITY SEG7 ISPORT ( CLK : IN STD_LOGIC ; K_AND : OUT INTEGER RANGE 31 DOWNTO 0 ; K1,K2 : OUT INTEGER RANGE 15 DOWNTO 0 ; LED7S01,LED7S10:OUT STD_LOGIC_VECTOR(0 TO 6));END ;ARCHITECTURE bhv_HL OF SEG7 ISSIGNAL Q1 : INTEGER RANGE 15 DOWNTO 0 ;SIGNAL Q2 : INTEGER RANGE 15 DOWNTO 0 ;SIGNAL Q3 : INTEGER RANGE 31 D