classfinalprep-ComputerScience.pdfVIP

Final Exam ? When: 8:00-10:00 am Thursday, May 10th ? Location: here (Carson 439) ? 1/3: midterm material – See lecture notes for midterm preparation ? 2/3: material since midterm ? 1 page of personal notes ? No electronic devices/books/other notes Andrew H. Fagg: Embedded RealTime Systems: Final Preparation Pre-Midterm Material ? Basic gates ? Boolean algebra ? Digital circuits and circuit reduction ? Number representations (binary, hex) ? Bit-wise operators ? Sequential logic ? Components of microprocessors ? Memory behavior (input/output signals, buses, addressing) Andrew H. Fagg: Embedded RealTime Systems: Final Preparation Key Microprocessor Components ? General- versus special-purpose registers ? Instruction decoder ? Data memory (RAM) ? Program memory (EEPROM in our case) ? I/O modules – Digital input/output – Serial UART Andrew H. Fagg: Embedded RealTime Systems: Final Preparation Special-Purpose Registers What does each do? ? Program counter ? Instruction register ? Status register Andrew H. Fagg: Embedded RealTime Systems: Final Preparation Timer/Counters ? Prescalars ? Counters (hardware) – Timer0, timer2: 8-bit – Timer1: 16-bit ? Interrupts on timerX overflow ? Computing timerX count frequencies/periods ? Computing timerX interrupt frequencies/periods Andrew H. Fagg: Embedded RealTime Systems: Final Preparation Interrupts ? What are they? ? Types of interrupts ? Interrupt service routines. Examples: – Pulse Width Modulation (PWM) – Producing digital signals of various frequencies (e.g., can introduce software counters, too) – Sensor control (sonar) – Serial buffering Andrew H. Fagg: Embedded RealTime Systems: Final Preparation Interrupt Woes The Shared Data Problem ? One segment of code can be interrupted at any time to execute another segment of code ? Both access the same data structures ? Solution: ensure that a critical section of code cannot be interrupted – In our case: use disable/enable interrupts Andrew H. Fagg: Embedded RealTime Systems: Final