计算机体系结构8.ppt

Branch InstructionsSima, Fountain and KacsukChapter 8 CSE3304 Major Chapter Goals To understand how to minimise the performance degradation of branches Basic approach to branch handling Delayed branching Branch processing Multi-way branching Guarded Execution Types of branch instructions Types of branch instructions Why worry about different types of branches? Branches cause stalls of pipelines Different techniques for minimizing branch effects Take advantage of different type of branch e.g. Unconditional branch ALWAYS occurs. Therefore, hardware can plan for the branch in advance. e.g. difference between loop closing and normal conditional Ways of checking condition Conditional branches need to evaluate a predicate Two main approaches Result state IBM 360, 370, PDP-11, VAX-11, x86, Pentium, MC68000, Sparc, PowerPC. Direct Check PDP-10, Cyber/70, PDP-8, CRAY, MIPS, HPPA, Dec Alpha Result State Result state is declared to hold status information related to result of operation Typical implementation is condition codes or flag registers which are updated after every arithmetic result is produced Conditional branch instructions interrogate the flags in subsequent instructions Result state disadvantages The generation of result state is not straightforward; irregular structure occupies additional chip area Makes pipeline longer Result state disadvantages ... Sequential in concept. How do we pack instructions in Superscalar and VLIW machine? Direct Check No result state is declared Specified conditions are directly checked by explicit instructions Conditional branching can be requested if the specified conditions are met. May involve one or two instructions Fits better into superscalar architectures Shorter clock cycle because only check when necessary Comparison of conditional branches The effect of branches Need to understand whether branches are taken or not Then tailor the architecture to perform fastest on most common case. It turns out that most branches