vcdpptdesignsol.ppt

  Virtuoso a Custom Designer (VCD)Product No. 3700  Custom IC Design Problem Custom IC physical design is a bottleneck Too many design iterations Need productivity gains in custom IC physical design Availability of Design Library or Design Kit Human transfer of design information from schematic or design package, prone to error Intensive and tedious manual layout of polygons Design iterations due to manual errors and ECOs AMS Market Dynamics : Old Manual methodology - tool flow ACPD methodology Difficulty in implementing automation Lack bandwidth (insufficient resources) Lack core competency (insufficient expertise) Schematic library symbols Virtuoso XL (connectivity) Skill code and ROD for parameterized cell (Pcell) development Tech files (layout editor, router, placer) DRC/LVS deck development develop a flow Develop a process design kit (PDK) Support and maintenance of the methodology/PDK Virtuoso? Custom Designer (VCD) What is VCD? Virtuoso? Custom Designer 1.0 (VCD) Point Tools ?????? VCD Solution What is in VCD? Single seat license Tools (executables) Virtuosoa XL (VXL) Virtuosoa Custom Placer (VCP) Virtuosoa Custom Router (VCR) Virtuosoa Power Router Diva DRC Diva LVS Assura DRC (VCD QSR) Assura LVS (VCD QSR) Generic PDK (GPDK) Methodology Guide Internet Learning Series (ILS) Maintenance What is a baseline foundry PDK? For example CMOS logic Composer logic symbol library N P mos, resistor and capacitor Pcells Virtuoso XL/VCP/VCR Tech and display files Assura/Diva DRC/LVS decks (download from foundry site) Foundries e.g. TSMC…., UMC… etc.. Technologies e.g. .18u, .25u…, Logic.., MS…., RF… etc.. Tested with VCD methodology Supported (maintenance available) Price book orderable item Cadence/TSMC Press Release (March 8, 2001) Cadence and TSMC Collaborate to Distribute Design Kits for Baseband and RF Foundry Silicon ``In the highly competitive communications market, time-to-volume is essential, said Michael Pawlik, TSMCs VP of Corporate Marketing. ``