浅诉FPGA.ppt

* Why can FPGAs accelerate computation? Because they have outrageous internal bandwidth, though over relatively few bits * * As this slide shows, serial connectivity is exploding in its usage. There has been a rapid migration from familiar parallel I/O standards such as PCI, RapidIO, Ethernet, and HyperTransport to serial protocols, especially Gigabit Ethernet and PCI Express. Most of the move has been because of the effective parallel bus limit of about one gigabit per second. This limit can be easily overcome with today’s high speed serial I/O standards, and for 2007 it is forecasted that serial I/O ports will outnumber parallel I/O ports overall across all electronic systems. * While a dedicated DSP chip executes operations at perhaps one gigahertz, it needs 250 clock periods to perform a 250-tap filter calculation. this limits it to 4 mega-samples per second. In the FPGA, these 250 operations can be executed simultaneously in one clock period. Even at the slower 500 MHz clock rate, the FPGA is thus over one hundred times faster than the dedicated DSP chip. * * * * * * * * * * * * * * * * In the past, systems were built with many discrete parts, including FPGAs, memory, and I/O. Logic design tools from a variety of suppliers were (and still are) used to specify individual functionality as well as integrating the parts to function together. The CPU side of the product was (and still is) most often a discrete part. The interfacing of the CPU to the logic, memory, and I/O systems is performed through the logic tools. The software side was (and still is) implemented with specialized tools for code and OS development. The hardware and software interfacing work is performed with a combination of these tools and, in some cases, co-verification or co-simulation tools. In the latter part of the 1990s, many of the logic functions became integrated into single devices, such as the 4K and Virtex? device families from Xilinx. Larger amounts of memory were still off chip,