0-国立交通大学资讯工程学系NCTUDepartmentofComputerScience.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 蔡文能 @交通大學資工系 More about Logical gates De Morgan theory Using NAND gates ONLY Using NOR gates ONLY Adder Half Adder Full Adder Karnaugh maps ? 蔡文能 @交通大學資工系 De Morgan theory (De Morgan Law) A NAND gate: A NAND is equivalent to an OR gate with two NOT gates A NOR gate can be constructed by using one AND gate with two Inverters (NOT gate) A B Y Y = A · B = A + B Y = A+B = A · B 蔡文能 @交通大學資工系 Using NAND Gates ONLY (1/2) It is possible to implement any boolean expression using only NAND gates X X NOT AND A B A·B A·B OR A A+B B 蔡文能 @交通大學資工系 Using NAND Gates ONLY (2/2) Example of NAND Gate representation Implement the following circuit using only NAND gates x3 x1 x2 Hint: using De Morgan theory 蔡文能 @交通大學資工系 Answer to previous page problem Tips: two NOTs together can be removed. A+B x3 x1 x2 A B A·B A·B A B AND feeding OR 蔡文能 @交通大學資工系 Using NOR Gates ONLY Similar pattern to using NAND gates A.B X X A B A.B A.B A A+B B X X A B A.B A+B A B OR AND NOT 蔡文能 @交通大學資工系 Half adder (do adding A, B) The sum is XOR operation The carry is their AND value A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 C A B S 蔡文能 @交通大學資工系 Full Adder Develop a truth table and Boolean expressions for the full adder (adding A, B, and Carry in.) Cin A B S C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sum Full adder A B Cin Cout 蔡文能 @交通大學資工系 A Full adder can be constructed using 2 half adder Sum Full adder A B Cout Cin Fig.B.2 in Appendix B 蔡文能 @交通大學資工系 A Full Adder using only NAND gates Sum 蔡文能 @交通大學資工系 Truth table for full adder Cin A B S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Hint: Complete the Karnaugh maps for the Sum and the Carry out columns 蔡文能 @交通大學資工系 Karnaugh maps for sum and carry AB Cin 00