关键词数字集成电路,功耗,便携式设备.PDFVIP

How to architect, design, implement, and verify low-power digital integrated circuits Andy Eliopoulos, Pinhong Chen, and Dr. Qi Wang, Cadence Design Systems 关键词：数字集成电路，功耗，便携式设备 In recent years, power consumption has moved to the forefront of digital integrated circuit (IC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Furthermore, with every new process generation, leakage power consumption increases at an exponential rate. It is common to think of low-power designs only in the context of handheld, battery-powered devices such as personal digital assistants (PDAs) and cell phones. And it is certainly fair to say that this class of device is at the top of low-power development concerns. In reality, however, power consumption (and corresponding heat generation) is also of significant interest to semiconductor segments with fixed installations, such as networking, set-top boxes, and computing devices. For example, the InformationWeek Power Surge article on 27 February 2006 reported that data center electricity costs are now in the range of US$3.3 billion annually, and it can cost more to cool a data center than it does to lease the floor space in which to house it. Additionally, consumers increasingly demand quieter devices for their living rooms and desktops, and low-power designs help manufacturers eliminate noisy cooling fans from set-top boxes and other products. Over recent years, a wide variety of techniques have been developed to address the various aspects of the power problem and to meet evermore-aggressive power specifications. These include (but are not limited to) the use of clock gating, multi-switching threshold (multi-Vt) transistors, multi-supply multi-voltage (MSMV), substrate biasing, dynamic voltage and frequency scaling (DVFS), and power shut-off (PSO). The power, timing, and area tradeoffs