数字逻辑44.pptVIP

* * Minimize by shared operation Binary Decoder and multiplexer Chapter 4 Combinational logic design principles How to make a minimal circuit ? Shared operation Minimal sum Minimal product Optimize the design with shared terms LSB+1 adder D3D2D1D0=Q3Q2Q1Q0+1 Optimize the design with shared terms Optimize the design with shared terms D3：9 D2：6 D1：3 D0：0 D3 = Q3Q2’+Q3Q1’+Q3Q0’+Q3’Q2Q1Q0 D2 = Q2Q1’+Q2Q0’+Q2’Q1Q0 D1 = Q1Q0’+Q1’Q0 D0 = Q0’ Optimize the design with shared terms D3：7 D2：5 D1：3 D0：0 D3 = Q3(Q2’+Q1’+Q0’)+Q3’Q2Q1Q0 D2 = Q2(Q1’+Q0’)+Q2’Q1Q0 D1 = Q1Q0’+Q1’Q0 D0 = Q0’ Optimize the design with shared terms cost：2+9 D3 = Q3Y2+Q3’Y2’ D2 = Q2Y1+Q2’Y1’ D1 = Q1Q0’+Q1’Q0 D0 = Q0’ Y1 = Q1’+Q0’ = (Q1Q0)’ Y2 = Q2’+Y1 = (Q2Y1’)’ Optimize the design with shared terms Binary Decoder 4-bit Decoder Only inverter be shared 4-bit Decoder Some decoder be shared Decoder with control 4-bit Decoder All the decoder be shared N=2k bit Decoder Each output only cost one standard gate BCD8421 Decoder Total : 20 BCD8421 Decoder Total : 17 BCD8421 Decoder Total : 16 Demultiplexer Data flow control in digital design Multiplexer Demultiplexer Decoder Control gates Multiplexer Memory control Multiplexer with TG Bus control with TG