七组合逻辑电路设计.PPTVIP

第七章 组合逻辑电路设计 组合逻辑电路设计方法（补充） 设计实例1：2输入“与非”门电路设计 设计方案1： LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nand2_1 IS PORT (a, b : IN STD_LOGIC; y : OUT STD_LOGIC); END ENTITY nand2_1; ARCHITECTURE nand OF nand2_1 IS BEGIN y=a NAND b; END ARCHITECTURE nand ; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY nand2_2 IS PORT (a, b : IN STD_LOGIC; y : OUT STD_LOGIC); END ENTITY nand2_2; ARCHITECTURE nand OF nand2_2 IS BEGIN PROCESS(a,b) IS VARIABLE comb :STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN comb:=a b; CASE comb IS WHEN 00 =y=1; WHEN 01 =y=1; WHEN 10 =y=1; WHEN 11 =y=‘0; WHEN OTHER =y=‘X; END CASE; END PROCESS; END ARCHITECTURE nand; 课堂练习 请用VHDL设计一个三输入与非门。 LIBRARY IEEE ； USE IEEE.STD_LOGIC_1164.ALL ； ENTITY NAND3 IS PORT(A, B, C : IN STD_LOGIC ； Q : OUT STD_LOGIC ) ； END ENTITY test1 ； ARCHITECTURE NAND OF NAND3 IS BEGIN Q = not（A and B and C）； END ARCHITECTURE test1 ； 7.2 编码器 优先编码器 7.3 选择器 7.5 求补器 7.6 三态门 参考74151的真值表，采用CASE语句结构编写的VHDL源代码如下 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux8 IS PORT(A2,A1,A0: IN STD_LOGIC; D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC; G:IN STD_LOGIC; Y: OUT STD_LOGIC; YB:OUT STD_LOGIC); END ENTITY mux8; ARCHITECTURE dataflow OF mux8 IS SIGNAL comb: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN comb = G A2 A1 A0; 用CASE语句设计8选1选择器 并置运算符“”用于位的连接，构成了四位长度位矢量 PROCESS (comb,D0,D1,D2,D3,D4,D5,D6,D7,G) IS BEGIN CASE comb IS WHEN 0000 = Y = D0; YB = NOT D0; WHEN 0001 = Y = D1; YB = NOT D1; WHEN 0010 = Y = D2;