Design Methodology for Customizable Programmable Processors.ppt

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Design Methodology for Customizable Programmable Processors.ppt

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Design Methodology for Customizable Programmable Processors

Design Methodology for Customizable Programmable ProcessorsBerkeley – Finland Day, Oct. 18, 2002 Prof. Jarmo Takala Institute of Digital and Computer Systems Tampere University of Technology Tampere, Finland Tel: +358 – 33115 3879; Email: jarmo.takala@tut.fi Outline Motivation Transport Triggered Architecture (TTA) Design Methodology for TTAs Research at TUT Conclusions Motivation Programmable processors often used in products using digital signal processing (DSP) Flexibility Ease of verification Traditionally DSP processor architectures have been developed based on average performance in several benchmark tasks (~100) User applications often contain only subset of total benchmarks Efficiency can be improved by customizing architecture according to given tasks Motivation DSP applications are often hard realtime constrained execution should be deterministic dynamic runtime behaviours should be avoided Static scheduling lends itself to DSP Current design complexities call for increase in designer productivity High level languages should be used DSP algorithms contain inherent parallelism Instruction level parallelism (ILP) should be maximized What is needed? Application driven design process with easy design space exploration Replace hardware complexity by software complexity Compiler driven process Use templated architecture Flexible heterogeneous function units Modular scalability Orthogonal compiler friendly Choices for Architecture Template VLIW Gained Popularity in DSP Transport Triggered Architecture VLIW drawbacks Bypass complexity Register file complexity Register file design restricts FU flexibility Operation encoding format restricts FU flexibility Reverse programming paradigm [H. Corporaal, 94] data transport ? operation Instruction set contains only a single instruction: move From VLIW to TTA TTA Datapath Function Units Operands written to operand registers (O) Operation performed when last operand written to trigger register (T) Pipeline synchronized