Implementing a TMDS Video Interface in the Spartan-6 FPGA.pdf

XAPP495 (v1.0) December 13, 2010 1 ? Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Summary Transition Minimized Differential Signaling (TMDS) is a standard used for transmitting video data over the Digital Visual Interface (DVI) and High-Definition Multimedia Interface (HDMI). Both interfaces are popular in a wide range of market segments including consumer electronics, audio/video broadcasting, industrial surveillance, and medical imaging systems. They are commonly seen in flat panel TVs, PC monitors, blue-ray players, video camcorders, and medical displays. This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan?-6 FPGAs. Introduction The DVI and HDMI protocols use TMDS at the physical layer. The TMDS throughput is a function of the serial data rate of the video screen mode being transmitted. This in turn determines the FPGA speed grade that must be used to support this throughput. After the Spartan-3A family, Xilinx has offered embedded electrically-compliant TMDS I/O allowing implementation of DVI and HDMI interfaces inside the FPGA. The operation theory for this is detailed in Video Connectivity Using TMDS I/O in Spartan-3A FPGAs [Ref 1]. The data throughput in that application note was maximized at 666 Mb/s in the fastest speed grade. The Spartan-6 FPGA on the other hand has made significant speed improvements. Table 1 shows the maximum throughput for each speed grade of the Spartan-6 FPGA. Common video screen modes corresponding to these data rates are listed in Table 2. Application Note: Spartan-6 Family XAPP495 (v1.0) December 13, 2010 Implementing a TMDS Video Interface in the Spartan-6 FPGA Author: Bob Feng T