Improving quasi-dynamic schedules through region slip.pdf

Improving quasi-dynamic schedules through region slip.pdf

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Improving quasi-dynamic schedules through region slip

Improving Quasi-Dynamic Schedules through Region Slip Francesco Spadini Brian Fahs Sanjay Patel Steven S. Lumetta Center for Reliable and High-Performance Computing Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Abstract Modern processors perform dynamic scheduling to achieve better utilization of execution resources. A sched- ule created at run-time is often better than one created at compile-time as it can dynamically adapt to specific events encountered at execution-time. In this paper, we examine some fundamental impediments to effective static schedul- ing. More specifically, we examine the question of why schedules generated quasi-dynamically by a low-level run- time optimizer and executed on a statically scheduled ma- chine perform worse than using a dynamically-scheduled ap- proach. We observe that such schedules suffer because of region boundaries and a skewed distribution of parallelism towards the beginning of a region. To overcome these limi- tations, we investigate a new concept, region slip, in which the schedules of different statically-scheduled regions can be interleaved in the processor issue queue to reduce the region boundary effects that cause empty issue slots. 1 Introduction Modern high-performance microprocessors incorporate dynamic scheduling to achieve good performance for multiple-issue implementations. A dynamic scheduler’s abil- ity to schedule instructions continuously based on dynami- cally variant conditions fuels its ability to effectively find par- allel instructions. This ability, however, comes at the cost of extra hardware complexity and energy expended per dy- namic instruction. Static scheduling, alternatively, requires less hardware complexity because the scheduling function is incorporated into code generation. Static schedules, however, are more susceptible to degradation in performance due to variances in run-time behavior, such as load latencies and control flow patterns. A mid

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