MICROPROCESSOR DESIGN ISSUES TO FULLY EXPLOIT SHRINKING FEATURE SIZES AND AVOID BEING OVERW.pdf

2Deep-submicron technology allows billions of transistors on a single die, poten- tially running at gigahertz frequencies. According to Semiconductor Industry Asso- ciation (SIA) projections,1 the number of tran- sistors per chip and the local clock frequencies for high-performance microprocessors will continue to grow exponentially in the near future, as Figure 1 illustrates. This ensures that future microprocessors will become ever more complex. However, physical and program behavioral constraints will limit the usefulness of this complexity. Physical constraints include inter- connect and device limits, as well as practical limits on power and cost. Program behavioral constraints result from program control and data dependencies, and from unpredictable events during execution. Other challenges include the need for advanced CAD tools to combat the negative effect of greater complexity on design time. Designers will also have to make improve- ments to preserve computational integrity, reliability, and diagnostic features. Successful implementations will depend on the proces- sor architect’s ability to foresee technology trends and understand the changing design trade-offs for specific applications, beginning with the differing requirements for client ver- sus server processors. This article discusses these trade-offs in light of industry projections and the many considerations affecting deep- submicron technology. Limits of technology scaling Improved microprocessor performance results largely from technology scaling, which lets designers increase the level of integration at higher clock frequencies. While current implementations use feature sizes of about 0.25 micron, devices with feature sizes small- er than 0.1 micron are expected in the next few years. Table 1 shows projected specifica- tions through 2012. As feature sizes shrink, device area shrinks roughly as the square of the scaling factor. Meanwhile, device propa- gation delay (under constant field assu