Modeling and Extraction of Nanometer Scale Interconnects Challenges and Opportunities (Invi.pdfVIP

Proceedings of the 23rd Advanced Metallization Conference (AMC), San Diego, CA, October 16-19, 2006. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited) Roberto Suaya, Rafael Escovar and Salvador Ortiz Mentor Graphics, 38334 St Ismier Cedex, Grenoble, France Kaustav Banerjee and Navin Srivastava Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA ABSTRACT We discuss interconnect parasitic extraction in the nanometer domain using the ITRS 2005 roadmap for future technology generations. Resistance becomes the dominant contribution for timing for local wires at 65 nm and beyond, a major qualitative change. For scaled wires, maintaining global wire routes within 1 clock period is expensive in terms of power consumption. An acceptable solution involves reverse scaling of global wires leading to RLC transmission line behavior which results in significant power savings. RLC transmission for scaled signal wires is otherwise negligible. INTRODUCTION The traditional gains in microprocessor performance with every technology node slowed down considerably in the transition from 130 to 90 nm. Latest developments at 65 nm node, however, show signs of recovery from this slowdown: Intel announced the Xeon server Tulsa processor, packing 1.3 billion transistors with an expected clock at 3.4 GHz and consumption at 150 watts [1], while IBM’s recent Power6 processor chip [2], is clocked at 5.6 GHz (13 FO4 design – see Section IV). The representative size of layout database for chips of the complexity mentioned above is O(100 Gbytes). With O(N) transistors, and a comparable number of wires, the number of possible electromagnetic couplings is O(N2). Since the computational cost of analyzing such a large number of electromagnetic interactions is prohibitive, filtering while doing extraction is mandatory so that such interactions are considered only where nec