Modeling and Extraction of Nanometer Scale Interconnects Challenges and Opportunities (Invi.pdf

Modeling and Extraction of Nanometer Scale Interconnects Challenges and Opportunities (Invi.pdf

  1. 1、本文档共11页,可阅读全部内容。
  2. 2、有哪些信誉好的足球投注网站(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
Modeling and Extraction of Nanometer Scale Interconnects Challenges and Opportunities (Invi

Proceedings of the 23rd Advanced Metallization Conference (AMC), San Diego, CA, October 16-19, 2006. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited) Roberto Suaya, Rafael Escovar and Salvador Ortiz Mentor Graphics, 38334 St Ismier Cedex, Grenoble, France Kaustav Banerjee and Navin Srivastava Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA ABSTRACT We discuss interconnect parasitic extraction in the nanometer domain using the ITRS 2005 roadmap for future technology generations. Resistance becomes the dominant contribution for timing for local wires at 65 nm and beyond, a major qualitative change. For scaled wires, maintaining global wire routes within 1 clock period is expensive in terms of power consumption. An acceptable solution involves reverse scaling of global wires leading to RLC transmission line behavior which results in significant power savings. RLC transmission for scaled signal wires is otherwise negligible. INTRODUCTION The traditional gains in microprocessor performance with every technology node slowed down considerably in the transition from 130 to 90 nm. Latest developments at 65 nm node, however, show signs of recovery from this slowdown: Intel announced the Xeon server Tulsa processor, packing 1.3 billion transistors with an expected clock at 3.4 GHz and consumption at 150 watts [1], while IBM’s recent Power6 processor chip [2], is clocked at 5.6 GHz (13 FO4 design – see Section IV). The representative size of layout database for chips of the complexity mentioned above is O(100 Gbytes). With O(N) transistors, and a comparable number of wires, the number of possible electromagnetic couplings is O(N2). Since the computational cost of analyzing such a large number of electromagnetic interactions is prohibitive, filtering while doing extraction is mandatory so that such interactions are considered only where nec

文档评论(0)

l215322 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档