Rate analysis for streaming applications with on-chip buffer constraints.pdf

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Rate analysis for streaming applications with on-chip buffer constraints.pdf

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Rate analysis for streaming applications with on-chip buffer constraints

In Proceedings of Asia South Pacific Design Automation Conference 2004 Yokohama, Japan, January 2004 Rate Analysis for Streaming Applications with On-chip Buffer Constraints Alexander Maxiaguine ETH Zu?rich maxiagui@tik.ee.ethz.ch Simon Ku?nzli ETH Zu?rich kuenzli@tik.ee.ethz.ch Samarjit Chakraborty National University of Singapore samarjit@.sg Lothar Thiele ETH Zu?rich thiele@tik.ee.ethz.ch Abstract— While mapping a streaming (such as multimedia or network packet processing) application onto a specified architec- ture, an important issue is to determine the input stream rates that can be supported by the architecture for any given map- ping. This is subject to typical constraints such as on-chip buffers should not overflow, and specified playout buffers (which feed au- dio or video devices) should not underflow, so that the quality of the audio/video output is maintained. The main difficulty in this problem arises from the high variability in execution times of stream processing algorithms, coupled with the bursty nature of the streams to be processed. In this paper we present a mathe- matical framework for such a rate analysis for streaming applica- tions, and illustrate its feasibility through a detailed case study of a MPEG-2 decoder application. When integrated into a tool for automated design-space exploration, such an analysis can be used for fast performance evaluation of different stream processing ar- chitectures. I. INTRODUCTION Lately, there has been a tremendous increase in portable and mobile devices running algorithms for processing streams of audio and video data, and sometimes network packets. These include hand-held computers and mobile phones, and it is expected that their usage will increase even more in the fu- ture. Such devices typically have very stringent constraints pertaining to cost, size, and power consumption, and have posed several challenges towards developing appropriate mod- els, methodologies, languages and tools for designing them