ug_altera_lvds.pdfVIP

Altera LVDS SERDES IP Core User Guide 2014.08.18 ug_altera_lvds Subscribe Send Feedback The Altera LVDS SERDES IP Core configures the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) blocks. The IP core also supports LVDS channels placement, legality checks, and LVDS channel-related rule checks. The Altera LVDS SERDES IP core is only available for Arria? 10 devices. For Arria V, Cyclone? V, and Stratix? V devices, follow the steps inMigrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores on page 25 to migrate your IP. Related Information ? LVDSSERDESTransmitter/Receiver (ALTLVDS_TXandALTLVDS_RX)MegafunctionsUserGuide Features You can configure the features of Altera LVDS SERDES IP core through the IP Parameter Editor in the Quartus? II software. The Altera LVDS SERDES IP core feature includes the ALTLVDS_RX and ALTLVDS_TX IP cores features supported in Stratix V devices, such as: ? Parameterizable data channel widths ? Parameterizable serializer/deserializer (SERDES) factors ? Registered input and output ports ? PLL control signals ? Dynamic phase alignment (DPA) mode ? Soft clock data recovery (CDR) mode Functional Modes This table lists the functional modes for the Altera LVDS SERDES IP core. Table 1: Functional Modes for the Altera LVDS SERDES IP Core DescriptionFunctional Mode In this mode, the IP core configures the SERDES block as a serializer. A PLL generates the fast clock (fclk) and load enable (loaden) signals. TX ISO 9001:2008 Registered ? 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras