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Yield-Aware Cache Architectures
Yield Factors
Parametric
Lithography-
based
Defect Density
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0.35
micron
0.25
micron
0.18
micron
0.13
micron
0.09
micron
Process Technology
N
om
in
al
Y
ie
ld
s
Defect Density
Lithography-based
Parametric
Yield
Yield-Aware Cache Architectures
Serkan Ozdemir Debjit Sinha* Gokhan Memik Jonathan Adams Hai Zhou
EECS Department, Northwestern University
{soz463, debjit, memik, jra760, haizhou}@
Abstract
One of the major issues faced by the semiconductor
industry today is that of reducing chip yields. As the process
technologies have scaled to smaller feature sizes, chip yields
have dropped to around 50% or less. This figure is expected
to decrease even further in future technologies. To attack
this growing problem, we develop four yield-aware
microarchitecture schemes for data caches. The first one is
called Yield-Aware Power-Down (YAPD). YAPD turns off
cache ways that cause delay violation and/or have excessive
leakage. We also modify this approach to achieve better
yields. This new method is called Horizontal YAPD (H-
YAPD), which turns off horizontal regions of the cache
instead of ways. A third approach targets delay violation in
data caches. Particularly, we develop a VAriable-latency
Cache Architecture (VACA). VACA allows different load
accesses to be completed with varying latencies. This is
enabled by augmenting the functional units with special
buffers that allow the dependants of a load operation to stall
for a cycle if the load operation is delayed. As a result, if
some accesses take longer than the predefined number of
cycles, the execution can still be performed correctly, albeit
with some performance degradation. A fourth scheme we
devise is called a Hybrid mechanism, which combines the
YAPD and the VACA. As a result of these schemes, chips
that may be tossed away due to parametric yield loss can be
saved. Experimental results demonstrate that the yield losses
can be reduced
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