YieldEnhancement_12052012.pdf

1 HsinChu December 5, 2012 ITRS - YE ITWG Conference in HsinChu December 5, 2012 Lothar Pfitzner lothar.pfitzner@iisb.fraunhofer.de 2 HsinChu December 5, 2012 Scope of Yield Enhancement ? Aspects – Manufacturing of integrated semiconductor devices: numerous processing steps building the 3D structure of the chip (e.g. 9 Cu and low – k interconnect layers for 32 nm) – Yield: percentage of operating chips at the end of the manufacturing process ? Components – Determination and control of contamination – Inspection of structures and critical dimensions – Model to predict and calculate yield based on historic contamination levels (particulate and metals) and defects (failures) – Determination of kill ratios: Correlation between defects and yield A bird’s-eye view of 0.128μm2 FinFET SRAM cells (post silicide formation) Toschiba, Gordon Moore: “There is no fundamental obstacle to achieving device yields of 100%.” (Electronics, 38 (8), 1965) 45 nm ramp production was the fastest Presented by Mark Bohr (Intel) 02/2009 3 HsinChu December 5, 2012 Example: Inspection for ‘More than Moore’ Applications ?More Moore? and ?More than Moore? technologies – power electronics – mechatronics – MEMS applications – packaging and assembly – 3 D integration Laboratory scale inspection setup fulfilling requirements of low cost components and large area inspection (4 mm *4 mm field of view at μm resolution) (example for 3D integration, EC BMBF funded project JEMSIP3D under contract ENIAC Call 2008 / 120016) Test layout routing lines (CEA Leti) 4 HsinChu December 5, 2012 Contamination Analysis for Manufacturing Control ? Drivers – ultra clean manufacturing – unintended contamination of layers – dimensional, structural and compositional information – depth resolved quantification – non-volatile organic surface contamination ? Analytical Techniques for