High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation.pdf

High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation.pdf

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High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation

High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation Jaan Raik Raimund Ubar Tallinn Technical University, Estonia Department of Computer Engineering Abstract In current paper, a novel high-level symbolic path activation technique for sequential circuit test generation is proposed. The technique has been implemented as a part of a hierarchical ATPG tool which utilizes internal representation of multi-level (register-transfer and structural levels) decision diagram models. Experiments show that the proposed method allows to reach high fault coverages for circuits with complex sequential structures in a very short time. 1. Introduction Several techniques for solving the problem of gener- ating tests for structural faults in sequential circuits have been proposed over the years. On the gate-level, a number of deterministic test generation algorithms [1, 2] have been implemented. However, the execution times are extremely long and for medium and large circuits mostly rather low fault coverages have been achieved. Better performance has been reported of simulation based approaches [3, 4]. The above approaches are fast for smaller circuits only and become ineffective when number of primary inputs and sequential depth of the circuit increase. Test generation approaches [5, 6] that rely on functional fault models only do not guarantee satisfactory structural level fault coverages. As a solution, hierarchical approaches have been proposed which take advantage of high level information while generating tests for gate level faults. Recently, promising results based on software testing techniques combined with low level test have been published in [9]. The approach offers high fault coverages for small and medium sized benchmark circuits but the test generation takes relatively much time. Furthermore, the authors do not offer any formal method for generating the high-level test frames and the time needed to generate the fram

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