- 1、本文档共5页,可阅读全部内容。
- 2、有哪些信誉好的足球投注网站(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
- 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载。
- 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation
High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation
Jaan Raik Raimund Ubar
Tallinn Technical University, Estonia
Department of Computer Engineering
Abstract
In current paper, a novel high-level symbolic path
activation technique for sequential circuit test
generation is proposed. The technique has been
implemented as a part of a hierarchical ATPG tool
which utilizes internal representation of multi-level
(register-transfer and structural levels) decision
diagram models. Experiments show that the proposed
method allows to reach high fault coverages for circuits
with complex sequential structures in a very short time.
1. Introduction
Several techniques for solving the problem of gener-
ating tests for structural faults in sequential circuits
have been proposed over the years. On the gate-level, a
number of deterministic test generation algorithms [1,
2] have been implemented. However, the execution
times are extremely long and for medium and large
circuits mostly rather low fault coverages have been
achieved. Better performance has been reported of
simulation based approaches [3, 4]. The above
approaches are fast for smaller circuits only and
become ineffective when number of primary inputs and
sequential depth of the circuit increase.
Test generation approaches [5, 6] that rely on functional
fault models only do not guarantee satisfactory
structural level fault coverages. As a solution,
hierarchical approaches have been proposed which take
advantage of high level information while generating
tests for gate level faults. Recently, promising results
based on software testing techniques combined with
low level test have been published in [9]. The approach
offers high fault coverages for small and medium sized
benchmark circuits but the test generation takes
relatively much time. Furthermore, the authors do not
offer any formal method for generating the high-level
test frames and the time needed to generate the fram
您可能关注的文档
- EXCEL 教程34章.pdf
- except_but_besides_except_for_区别.ppt
- Exchange and the Coulomb blockade Peak height statistics in quantum dots.pdf
- eXist An Open Source Native XML Database.pdf
- Existence of extremal Beltrami coefficients with non-constant modulus.pdf
- Exclusive charm production in pbar p collisions at s^12 15 GeV.pdf
- expimp 与 expdp impdp 对比 及使用中的一些优化事项 ..pdf
- Exploiting path diversity in the link layer in wireless ad hoc networks.pdf
- Experimental behaviour of partially loaded concrete filled double-skin steel tube (CFDST) sections.pdf
- Exploration of acoustic correlates in speaker selection for concatenative synthesis.pdf
最近下载
- 兵工科技2014-14.pdf
- DL T 5745-2016 电力建设工程工程量清单计价规范.docx VIP
- 运单填写规范.ppt
- 岗位风险告知卡(挖掘机、装载机司机岗位).docx VIP
- 西师大版四年级上册数学第七单元 三位数除以两位数的除法 测试卷(突破训练)word版.docx
- 党团基本知识学习与社会实践思想报告【4篇】.docx VIP
- 文华财经指标公式源码WH6指标公式期货软件指标画线指标公式.doc
- 征地应急预案共5篇.docx VIP
- 精品解析:2024年天津市部分区中考二模语文试题(解析版).docx VIP
- 2022儿科副护士长竞聘职位PPT简医院儿科副护士长岗位竞聘自我介绍PPT课件(带内容).pptx
文档评论(0)