On Completely Robust Path Delay Fault Testable Realization of Logic Functions.pdf

On Completely Robust Path Delay Fault Testable Realization of Logic Functions V. A. Vardanian Institute of Informatics and Automation Problems Armenian National Academy of Sciences Yerevan, ARMENIA, 375044 Abstract A large class of Boolean functions, as well as almost all symmetr ic Boolean functions, are shown to have no two-level completely robust path-delay-fault testable ( R P D F T ) realization b y combinational circuits. Exact and asymptotic formulae are derived fo r the number of symmetric Boolean functions which have two-level completely R P D F T realization. To achieve completely R P D F T realization, a notion of RPDFT-ex tens ion as proposed f o r logic functions which have no two-level completely R P D F T realization. Algorithms are de - vised fo r the design o f RPDFT-extensions with at most 2 extra input variables. 1 Introduction Correct operation of high-speed VLSI circuits re- qires at-speed and reliable detection of delay faults which may change the temporal behavior of the cir- cuit without affecting its logical behavior. In order to avoid the occurrence of testing invalidation by haz- ards and to increase the reliability of a twepattern test for a path-delay-fault, an additional requirement was introduced in [l] tha t the fault be detected inde- pendently of delays in the rest of the circuit. Such tests were called robust tests in [a] where necessary and sufficient conditions were derived for the existence of robust tests for path delay faults. In [3],[4] it has been shown that many of the op- erations of algebraic factorization developed in mod- ern logic optimization tools [5] retain the robust path-delay-fault testability of two-level circuits. A synthesis-oriented approach was proposed in [4], based on two-level logic minimization and algebraic factor- ization procedures, t o obtain multilevel circuits of higher testability. However, this approach is not al- ways effective since the