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PT_S13W1_02
Agenda: Day One
Clock Constraints
1
Timing Exceptions
2
Timing Analysis Techniques
3
Scripting: Collections and Procedures
4
Unit Objectives
Define what are timing exceptions
State the legal start and end points for timing exceptions
State the command which reports ignored timing exceptions
Given a multicycle path and specifications, apply a multicycle path constraint
After completing this unit, you should be able to:
Using Timing Exceptions
What Are Timing Exceptions?
Timing exceptions are used to override the default single-cycle constraints described by create_clock, set_input_delay, and set_output_delay
Related Commands
set_false_path
set_multicycle_path
set_max_delay
set_min_delay
Removes timing constraints from that timing path
Allows more than one clock cycle for a timing path
Specifies max and min delays
Verifies any timing exceptions placed on a design
Restores the default timing constraints on specified paths
report_exceptions
reset_path
Legal Start and End Points for Exceptions
Timing exceptions must be placed from and to existing timing points
Legal Timing Start End Points
Start End
End
Start
For intermediate points in the timing path use the -through option
Reduce the Number of Timing Exceptions
To reduce the time to verify correct timing exceptions and analysis time; minimize the total number of exceptions.
The path from Q2_reg to Q3_reg is a false path; it is used for test purposes only. How many exceptions do each of the following represent?
set_false_path -from Q2_reg[*]/CP -to Q3_reg[*]/D
set_false_path -from Q2_reg[*]/CP
set_false_path -from clk2 -to clk3
2
1
4
Using the -through Option
The -through option requires more CPU for large designs
Do not use -through unless it is necessary
set_false_path -from U1/CP -through U2/A -through U3/B
-through U4/A -through U5/C -to U6/D
Sub-Optimal:
Optimal:
set_false_path -to U6/D
To help PT’s run time, use -to option when possible
Disabled Arcs Instead of False Paths
Use set_disabl
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