sn74lvc4245a具有三态输出的八路总线收发器和 3.3V 至 5V 移位器.pdf

FEATURES DESCRIPTION/ORDERING INFORMATION DB, DW, OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 (5 V) VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND VCCB (3.3 V) VCCB (3.3 V) OE B1 B2 B3 B4 B5 B6 B7 B8 GND SN74LVC4245A OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS SCAS375H–MARCH 1994–REVISED MARCH 2005 ? Bidirectional Voltage Translator ? 5.5 V on A Port and 2.7 V to 3.6 V on B Port ? Control Inputs V IH /V IL Levels Are Referenced to V CCA Voltage ? Latch-Up Performance Exceeds 250 mA Per JESD 17 ? ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has V CCB , which is set at 3.3 V, and A port has V CCA , which is set at 5 V. This allows for translation from a 3.3-V to a 5-V environment, and vice versa. br/ The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by V CCA . The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin 245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A to align with the conventional 245 pinout. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74LVC4245ADW SOIC – DW LVC4245A Reel of 2000 SN74LVC4245ADWR SSOP – DB Reel of 2000 SN74LVC4245ADBR LJ245A –40°C to 85°C Tube of 60 SN74LVC4245APW TSSOP – PW Reel of 2000 SN74LVC4245APWR LJ245A Reel of 250 SN74LVC4245APWT (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design gu