些fir源程序.docVIP

1、利用乘法器实现的4阶FIR程序（无符号的） module FirGen(clk,Load_x,x_in,c_in,y_out);parameter W1=9,//input bit length W2=18,//Multiplier bit width 2*W1 W3=19,//Adder width = W2+log2(L)-1 W4=11,//Output bit width L =4,//Filter length Mpipe=3;//Pipeline steps of muliplierinput clk,Load_x;//std_logicinput[W1-1:0] x_in,c_in;//inputsoutput[W3-1:0] y_out;//Resultsreg[W1-1:0] x;wire[W3-1:0] y;reg[W1-1:0] c0,c1,c2,c3;//Coefficient arraywire[W2-1:0] p0,p1,p2,p3;//Product arrayreg[W3-1:0] a0,a1,a2,a3;//Adder arraywire[W2-1:0] sum;//Auxilary signalswire clken,aclr;assign sum=0;assign aclr=0;assign clken=0;//--Load Data or CoefficientHYPERLINK mailto:always@(posedgealways@(posedge clk)begin:Loadif(!Load_x) begin c2=c_in; c2=c3; c1=c2; c0=c1; endelse begin x=x_in;//Get one data sample at a time endend//---Computer sum of products (SOP)HYPERLINK mailto:always@(posedgealways@(posedge clk)begin:SOP//computer the transposed filter additionsa0={p0[W2-1],p0}+a1;a1={p1[W2-1],p1}+a2;a2={p1[W2-1],p2}+a3;a3={p3[W2-1],p3};//First Tap has only a registerendassign y=a0;//Instantiate L piplelined multiplierlpm_mult mul_0 //Multiply x*c0=p0;(.clock(clk),.dataa(x),.datab(c0),.result(p0));defparam mul_0.lpm_widtha=W1;defparam mul_0.lpm_widthb=W1;defparam mul_0.lpm_widthp=W2;defparam mul_0.lpm_widths=W2;defparam mul_0.lpm_pipeline=Mpipe;defparam mul_0.lpm_representation=W1;lpm_mult mul_1 //Multiply x*c0=p0;(.clock(clk),.dataa(x),.datab(c1),.result(p1));/*To be added*/lpm_mult mul_2 //Multiply x*c0=p0;(.clock(clk),.dataa(x),.datab(c2),.result(p2));/*To be added*/lpm_mult mul_3 //Multiply x*c0=p0;(.clock(clk),.dataa(x),.datab(c3),.result(p3));/*To be added*/assign y_out=y[W3-1:W3-W4];endmodule 2、利用符号拓展以及移位实现的4抽头直接FIR滤波器 module FirSrg();input clk;input[7:0] x;output[7:0] y;reg[7:0] u;//Tapped delay line array of bytesreg[7:0] tap0,tap1,tap2,tap3;//For bit access use single vectors in