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LatticeispLEVERintegrationwithAldecActive
Lattice ispLEVER integration with Aldec Active-HDL - Mixed Tutorial
Introduction
This Tutorial is created to help you become familiar with integrating the Aldec Active-HDL simulator with Lattice ispLEVER. No prior knowledge of HDL simulation tools is required, but elementary knowledge of VHDL and Verilog will be helpful.
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If you want to refresh your VHDL/Verilog, you are welcome to use our Interactive Tutorials: just go to the Help menu in Active-HDL GUI, and then select the Interactive VHDL Tutorial or Interactive Verilog Tutorial option. The same tutorial is also accessible directly from the installation CD.After this tutorial, you will be able to launch Active-HDL simulator from ispLEVER, compile, run and debug functional simulation as well as post-route timing simulation.
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Configuring to launch Aldec Active-HDL simulator
1.?????? Double-click the ispLEVER icon on your desktop.
2.?????? Click on the Options tab in the GUI and from the drop-down menu click Environment.
3.?????? The Environment Options dialog should now be in focus. Select Directories tab.
4.??????? As shown in Fig. 1, in the ‘Active-HDL:’ field, browse to the following location “C:\PROGRAM FILES\ALDEC\ACTIVE-HDL 7.2\BIN” or the path where Active-HDL is installed on your machine. Click OK to close the Environment Options dialog.
Fig. 1: Configuring ispLEVER to use Active-HDL
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Note: To complete this tutorial you need to use either Mentor Precision or full version of Synplicity
Synplify? synthesis tool. Synplicity Synplify for Lattice does not support mixed designs.
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5.?????? Select Options from the main menu and click Select RTL Synthesis or Simulator… A new dialog box will appear. Make sure the settings are as shown in Fig. 2. Click OK.
Fig. 2: Selecting default simulator
Note: You may skip the above step if only one synthesis tool and one simulator are installed, as all other options will be masked.
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Creating a New Project in ispLEVER
In this tutorial we will be dealing with mixed VHDL/V
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