VHDL2Identifiersdataobjectsanddatatypes課件.pptVIP

Integer type (depends on your tool; it uses large amount of logic circuits for the implementation of integer/float operators) E.g. Range from -(2^31) to (2^31)-1 VHDL 2. Identifiers, data objects and data types ver.5a * Floating type -3.4E+38 to +3.4E+38 For encoding floating numbers, but usually not supported by synthesis tools of programmable logic because of its huge demand of resources. VHDL 2. Identifiers, data objects and data types ver.5a * Enumeration types: How to input an abstract concept into a circuit ? E.g.1 color: red, blue, yellow, orange etc, we need 2 bits E.g.2 Language type: Chinese, English, Spanish, Japanese, Arabic. How many bits needed? Answer: 5 different combinations: 3 bits 中文字, Chinese characters, caracteres chinos,漢字,?????? ??????? , VHDL 2. Identifiers, data objects and data types ver.5a * Enumeration types: An enumeration type is defined by listing (enumerating) all possible values Examples: type COLOR is (BLUE, GREEN, YELLOW, RED); type MY_LOGIC is (’0’, ’1’, ’U’, ’Z’); -- then MY_LOGIC can be one of the 4 values VHDL 2. Identifiers, data objects and data types ver.5a * VHDL 2. Identifiers, data objects and data types ver.5a * Exercises 2.5 Example of the enumeration type of the menu of a restaurant: type food is (hotdog, tea, sandwich, cake, chick_wing); (a) Declare the enumeration type of the traffic light. Answer: _______________________________________ (b) Declare the enumeration type of the outcomes of rolling a dice. Answer: _______________________________________ (c) Declare the enumeration type of the 7 notes of music. Answer: _______________________________________ DEFINE Array or a bus VHDL 2. Identifiers, data objects and data types ver.5a * Std_logic_vector (array of bits) for bus implementation To turn bits into a bus ‘bit’ or ‘std_logic’ is ‘0’, ‘1’ etc. Std_logic_vector is “000111”etc. 1 entity eqcomp3 is 2 port (a, b: in std_logic_vector(2 downto 0); 3 equals: out std_logic); 4 end eqcomp3; So a, b are 3-bit v