I2C主控器细则,英语.doc

I2C-Master Core Specification Author: Richard Herveille rherveille@opencores.org Rev. 0.9 July 3, 2003 1 Introduction I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. The interface defines 3 transmission speeds: - Normal: 100Kbps - Fast: 400Kbps - High speed: 3.5Mbps Only 100Kbps and 400Kbps modes are supported directly. For High speed special Ios are needed. If these IOs are available and used, then High speed is also supported. FEATURES ??Compatible with Philips I2C standard ??Multi Master Operation ??Software programmable clock frequency ??Clock Stretching and Wait state generation ??Software programmable acknowledge bit ??Interrupt or bit-polling driven byte-by-byte data-transfers ??Arbitration lost interrupt, with automatic transfer cancelation ??Start/Stop/Repeated Start/Acknowledge generation ??Start/Stop/Repeated Start detection ??Bus busy detection ??Supports 7 and 10bit addressing mode ??Operates from a wide range of input clock frequencies ??Static synchronous design ??Fully synthesizable 2 IO ports 2.1 Core Parameters 2.1.1 ARST_LVL The asynchronous reset level can be set to either active high (1’b1) or active low (1’b0). 2.2 WISHBONE interface signals The core features a WISHBONE RevB.3 compliant WISHBONE Classic interface. All output signals are registered. Each access takes 2 clock cycles. arst_i is not a WISHBONE compatible signal. It is provided for FPGA implementations. Using [arst_i] instead of [wb_rst_i] can result in lower cell-usage and higher performance, because most FPGAs provide a dedicated asynchronous reset path. Use either [arst_i] or [wb_rst_i], tie the other to