A25Gbs5.8mWCMOSEqualizer.PDF

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 2, FEBRUARY 2015 515 A 25 Gb/s 5.8 mW CMOS Equalizer Jun Won Jung and Behzad Razavi, Fellow, IEEE Abstract—Low-power equalization remains in high demand for fails to represent the practical value of a design. It is possible to wireline receivers operating at tens of gigabits per second in copper de?ne a ?gure of merit (FOM) accounting for the channel loss media. This paper presents a design incorporating a continuous- [11] but this FOM has not been widely adopted. time linear equalizer and a two-tap half-rate/quarter-rate deci- sion-feedback equalizer that exploits charge steering techniques to The development of an equalizer entails several design reduce the power consumption. Realized in 45 nm technology, the choices. prototype draws 5.8 mW from a 1 V supply and compensates for 1) The number of stages in and the boost factor provided 24 dB of loss with . by the CTLE: the larger these parameters, the higher the Index Terms—Charge steering, decision feedback, equalizer, CTLE power consumption and, at high speeds, the larger linear equalizer, nonlinearity. the number of inductors; as explained in this paper, the DFE power consumption in our work is reduced so much that it is now less than that of the CTLE, a point of sharp I. INTRODUCTION contrast to the prior art [1], [3], [5]. 2) The choice of direct DFE versus loop unrolling: the latter HE demand for high-speed, low-power serial links con- replaces the summing junction s