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译码器 74HC154
M4C5/M4C5 -o1 ieDecoder Line 4-to-16 MM54HC154/MM74HC154
September 1990
MM54HC154/MM74HC154
4-to-16 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol- Each output can drive 10 low power Schottky TTL equiva-
ogy, and is well suited to memory address decoding or data lent loads, and is functionally and pin equivalent to the
routing applications. It possesses high noise immunity, and 54LS154/74LS154. All inputs are protected from damage
low power consumption of CMOS with speeds similar to low due to static discharge by diodes to VCC and ground.
power Schottky TTL circuits.
The MM54HC154/MM74HC154 have 4 binary select inputs Features
(A, B, C, and D). If the device is enabled these inputs deter- Y Typical propagation delay: 21 ns
mine which one of the 16 normally high outputs will go low. Y Power supply quiescent current: 80 mA (74HC)
Two active low enables (G1 and G2) are provided to ease
Y Wide power supply voltage range: 2–6V
cascading of decoders with little or no external logic.
Y Low input current: 1 mA maximum
Connection Diagram Dual-In-Line Package
TL/F/5122–1
Top View
Order Number MM54HC154 or MM74HC154
Truth Table
Inputs Low
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